問答

如何配置MIPI DSI Clock和PCLK

提問者： 匿名人士66325 2017-06-23 00:00

最佳答案

RK針對MIPI DSI的lcd配置時有兩個clock, rockchip,dsi_hs_clk 和 clock-frequency.文件中如下:disp_mipi_init: mipi_dsi_init{compatible = "rockchip,mipi_dsi_init";rockchip,screen_init = <1>;rockchip,dsi_lane = <4>;rockchip,dsi_hs_clk = <348>;rockchip,mipi_dsi_num = <1>;};disp_timings: display-timings {native-mode = <&timing0>;compatible = "rockchip,display-timings";timing0: timing0 {screen-type = ;lvds-format = ;out-face = ;clock-frequency = <58200000>;hactive = <480>;vactive = <1280>;hback-porch = <160>;hfront-porch = <160>;vback-porch = <10>;vfront-porch = <12>;hsync-len = <24>;vsync-len = <2>;hsync-active = <0>;vsync-active = <0>;de-active = <0>;pixelclk-active = <0>;swap-rb = <0>;swap-rg = <0>;swap-gb = <0>;};};有人可能對這兩個值不太清楚如何設(shè)置,而設(shè)置出錯會引起顯示異常,這里簡要說明下:clock-frequency:即DCLK(dotc clock), PCLK(pixel clock).clock-frequency = (h_active + hfp + hbp + h_sync) * (v_active + vfp + vbp + v_sync) * fps廠商給的參考值是58.2MHz, 那么fps就是:fps = 58200000 / (480 + 160 + 160 +24) * (1280 + 12 + 10 + 2) = 54HzPCLK不能太大,Android支持不超過60fps.PCLK不能太小,小了畫面刷新率會比較慢.rockchip,dsi_hs_clk:即每條MIPI data lane 傳輸速率.dsi_hs_clk = ((h_active + hfp + hbp + h_sync) * (v_active + vfp + vbp + v_sync) * fps * bpp) / lane_number這里就是:dsi_hs_clk = ((480 + 160 + 160 +24) * (1280 + 12 + 10 + 2) * 54 * 24) / 4 = 348136704 bps = 348 Mbpshs_clk不能太小,太小會顯示灰屏,偏小會偏移.hs_clk不能太大,過大畫面會顯示條紋.RK文檔有提到 dsi_hs_clk還需要加上100, 追蹤了下源碼,沒看出來.另外我有實際測試其中一款屏,發(fā)現(xiàn)最終的值還是會有差異,不知道這是為什么.順便說下, 由于MIPI DSI上升沿和下降沿都可以發(fā)送數(shù)據(jù),所以MIPI CLK Lane * 2 = MIPI DATA Lane在測量的時候, 要注意MIPI DSI CLK Lane的時鐘速率會慢一倍.

回答者：huangjiahua112017-06-25 00:00

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